A. Field of the Invention
This invention relates to digital waveform processing and, more particularly, to phase detection between two digital waveforms.
B. Description of the Prior Art
In phase-locked systems, phase detectors are commonly used in feedback loops to determine the phase relationship between clocks such as a reference clock and a delayed clock. Using phase detectors to detect the phase differences between the reference clock and the delayed clock, negative feedback can be used to null differences in phase between the two clock signals.
If a digital phase detector senses that the delayed clock precedes the reference clock, the delayed clock has negative phase with respect to the reference clock and is therefore said to lead the reference clock. Conversely, if the digital phase detector senses that the delayed clock follows the reference clock, the delayed clock has positive phase with respect to the reference clock and is therefore said to lag the reference clock.
Accordingly, digital phase detectors generally receive two inputs, REFCLK and DLYCLK, which correspond with the reference clock and delayed clock signals. Furthermore, digital phase detectors often generate two outputs, LEAD and LAG, which correspond with negative and positive phase relationships between the two input signals, respectively. When there is a negative phase relationship between the two input signals, i.e. the delayed clock precedes the reference clock, the digital phase detector outputs an active LEAD signal or an inactive LAG signal. On the other hand, when there is a positive phase relationship between the two input signals, i.e. the reference clock precedes the delayed clock, the digital phase detector outputs an active LAG signal or an inactive LEAD signal.
An important characteristic of an ideal digital phase detector is identical processing for each of the two input signals. Identical processing, or perfect symmetry, is necessary in order to minimize the possibility of introducing any errors into phase measurements between the two inputs, REFCLK and DLYCLK. If a digital phase detector has asymmetric processing for the REFCLK and DLYCLK inputs, incorrect LEAD and LAG outputs may be generated by the phase detector. In contrast, an ideal digital phase detector with perfectly symmetric processing should introduce minimal error into phase measurements between the two inputs, even when the phase differences between the two signals are very small.
Many prior art digital phase detectors suffer from effects associated with their lack of symmetric circuitry. As a result, these prior art phase detectors inadvertently introduce errors into their phase measurements which may result in incorrect LEAD and LAG outputs.
Other prior art digital phase detectors may have symmetric circuitry, but these phase detectors have limited usefulness since their LEAD and LAG outputs are only valid for fractions of a clock period. In addition, many of these prior art detectors are limited to detecting phase differences between input waveforms which have the same frequency. Digital waveform synthesizers, such as the one described in pending patent application, Ser. No. 08/394,174, filed on Feb. 24, 1995 and entitled "DELAY INTERPOLATION CIRCUITRY," require digital phase detectors capable of detecting phase differences between input waveforms having different frequencies.
Therefore, a digital phase detector having symmetric circuitry, having LEAD and LAG outputs that are valid for an entire clock period, and capable of detecting phase differences between input waveforms having different frequencies is desired.